在 2023/8/25 20:56, Krzysztof Kozlowski 写道:
[...]
How did you sneak this property? The version - v2 - which was reviewed
by Rob:
https://lore.kernel.org/all/20190905144316.12527-7-jiaxun.yang@xxxxxxxxxxx/
did not have it.
Now v3 suddenly appears with Rob's review and this property:
https://lore.kernel.org/all/20200112081416.722218-4-jiaxun.yang@xxxxxxxxxxx/
Please help me understand this property appeared there and how did you
get it reviewed?
Hi all,
It has been some years since this series was merged.
My vague memory tells me there was some off-list discussion made in IRC with
linux-arch folks and IRQ folks to come up with this binding design.
In this case I guess I forgot to drop Rob's R-b tag when updating this patch
between reversions. I apologize for any inconvenience this may have caused.
<0xffffffff>, /* int1 */
<0x00000000>, /* int2 */
<0x00000000>; /* int3 */
So now you will keep bringing more hacks for a hacky property. No, this
cannot go on.
What's the best way, in your opinion, to overhaul this property? As we don't
really care backward compatibility of DTBs on those systems we can just
redesign it.
A little bit background about this property, LIOINTC can route a
interrupt to any of
4 upstream core interrupt pins. Downstream interrupt devicies should not
care about
which pin the interrupt go but we want to leave a knob in devicetree for
performance
tuning. So we designed such property that use masks corresponding to
each upsteam
interrupt pins to tell where should a interrupt go.
Thnaks
- Jiaxun
Best regards,
Krzysztof
