Hi Linus, let me appologize for walking into dark past :) Here's some more context for a start: https://www.mail-archive.com/linux-kernel@xxxxxxxxxxxxxxx/msg1691602.html (note that "OK phew then I'm safe" ;-)) After moving a few Octeon 70XX based boards from vendor based 4.9 kernel to 6.1 mainline a huge drop of MMC performance was observed. While running badblocks on 2G partition takes 1min (±5s) and about 35k interrupts on 4.9, recent kernels need over 3mins and 500k+ interrupts. How do we get there? ff4143ccff31 ("MIPS: Octeon: cavium_octeon_defconfig: Enable Octeon MMC") enabled MMC driver, but left MMC_BLOCK_BOUNCE disabled, although driver performace depends on it. c3dccb74be28 ("mmc: core: Delete bounce buffer Kconfig option") Added MMC_CAP_NO_BOUNCE_BUFF to the caps, based on assumption it should be there as MMC_BLOCK_BOUNCE is disabled in defconfig de3ee99b097d ("mmc: Delete bounce buffer handling") finally removed all bounce buffer handling as almost nothing needs that. Sadly, 70XX SoC cannot do SG, so it suffers a lot. Strangely enough, above patches are either authored or suggested by Cavium's employees. So, given the number of affected SoC and before cooking driver specific solution, are we sure we indeed do not want some generic one? While there, you might consider following patch: -- >8 -- From: Ladislav Michl <ladis@xxxxxxxxxxxxxx> Subject: [PATCH] mmc: cavium: Remove misleading comment Comment about disabling bounce buffers was added with c3dccb74be28 ("mmc: core: Delete bounce buffer Kconfig option") and should be deleted with de3ee99b097d ("mmc: Delete bounce buffer handling"). For the record, this driver should have never been used MMC_CAP_NO_BOUNCE_BUFF as it hits performance badly for non SG capable SoC. Signed-off-by: Ladislav Michl <ladis@xxxxxxxxxxxxxx> Fixes: de3ee99b097d ("mmc: Delete bounce buffer handling") --- drivers/mmc/host/cavium.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/mmc/host/cavium.c b/drivers/mmc/host/cavium.c index b58f003b10a4..71a9f91d2fc6 100644 --- a/drivers/mmc/host/cavium.c +++ b/drivers/mmc/host/cavium.c @@ -1032,8 +1032,6 @@ int cvm_mmc_of_slot_probe(struct device *dev, struct cvm_mmc_host *host) * We only have a 3.3v supply, we cannot support any * of the UHS modes. We do support the high speed DDR * modes up to 52MHz. - * - * Disable bounce buffers for max_segs = 1 */ mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_CMD23 | MMC_CAP_POWER_OFF_CARD | MMC_CAP_3_3V_DDR; -- 2.39.2
