On Mon, Jul 31, 2023, Ladislav Michl wrote:
> From: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
>
> It might be interesting to know control register value in case
> clock fails to enable.
Please also note that you did a minor reformat too.
>
> Signed-off-by: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@xxxxxxxxxx>
> ---
> CHANGES:
> - v4: new patch
> - v5: Philippe's review tag
>
> drivers/usb/dwc3/dwc3-octeon.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c
> index 330bcb59cc95..d578110f7afb 100644
> --- a/drivers/usb/dwc3/dwc3-octeon.c
> +++ b/drivers/usb/dwc3/dwc3-octeon.c
> @@ -299,8 +299,8 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
> val = dwc3_octeon_readq(uctl_ctl_reg);
> if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) ||
> (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) {
> - dev_err(dev, "dwc3 controller clock init failure.\n");
> - return -EINVAL;
> + dev_err(dev, "clock init failure (UCTL_CTL=%016llx)\n", val);
> + return -EINVAL;
> }
>
> /* Step 4c: Deassert the controller clock divider reset. */
> --
> 2.39.2
>
Acked-by: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx>
Thinh
