From: Rafał Miłecki <rafal@xxxxxxxxxx>
Use order as specified in the binding (first "ethif" then "fe").
This fixes:
arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: ethernet@1e100000: clock-names:0: 'ethif' was expected
From schema: Documentation/devicetree/bindings/net/mediatek,net.yaml
arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: ethernet@1e100000: clock-names:1: 'fe' was expected
From schema: Documentation/devicetree/bindings/net/mediatek,net.yaml
Fixes: 7a6ee0bbab25 ("mips: dts: ralink: add MT7621 SoC")
Signed-off-by: Rafał Miłecki <rafal@xxxxxxxxxx>
---
arch/mips/boot/dts/ralink/mt7621.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index 7caed0d14f11..73035d4f4cc1 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -300,9 +300,9 @@ ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
- clocks = <&sysc MT7621_CLK_FE>,
- <&sysc MT7621_CLK_ETH>;
- clock-names = "fe", "ethif";
+ clocks = <&sysc MT7621_CLK_ETH>,
+ <&sysc MT7621_CLK_FE>;
+ clock-names = "ethif", "fe";
#address-cells = <1>;
#size-cells = <0>;
--
2.35.3
