On Sat, May 20, 2023, at 16:45, Maciej W. Rozycki wrote:
> if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
> *__mem = __val; \
> else if (cpu_has_64bits) { \
> unsigned long __flags; \
> type __tmp; \
> \
> if (irq) \
> local_irq_save(__flags); \
> __asm__ __volatile__( \
> ".set push" "\t\t# __writeq""\n\t" \
> ".set arch=r4000" "\n\t" \
> "dsll32 %L0, %L0, 0" "\n\t" \
> "dsrl32 %L0, %L0, 0" "\n\t" \
> "dsll32 %M0, %M0, 0" "\n\t" \
> "or %L0, %L0, %M0" "\n\t" \
> "sd %L0, %2" "\n\t" \
> ".set pop" "\n" \
> : "=r" (__tmp) \
> : "0" (__val), "m" (*__mem)); \
> if (irq) \
> local_irq_restore(__flags); \
> } else \
> BUG(); \
>
> etc. so we don't actually lose atomicity, because we always use 64-bit
> operations (SD above, store-doubleword) and we BUG if they are not there
> (i.e. with 32-bit hardware; not a build-time check as in principle the
> same 32-bit kernel image ought to run just fine both on 32-bit and 64-bit
> hardware). A few MIPS platforms do use them, e.g. SB1250, which requires
> 64-bit unswapped accesses to SoC registers.
Ok, makes sense.
Arnd
