On Monday, 22 February 2016 19:09:44 CET Paul Burton wrote: > Index-based cache operations may be arbitrarily reordered by out of > order CPUs. Thus code which writes back the dcache & then invalidates > the icache using indexed cache ops must include a barrier between > operating on the 2 caches in order to prevent the scenario in which: > > - icache invalidation occurs. > > - icache fetch occurs, due to speculation. > > - dcache writeback occurs. > > If the above were allowed to happen then the icache would contain stale > data. Forcing the dcache writeback to complete before the icache > invalidation avoids this. > > Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx> > Cc: James Hogan <james.hogan@xxxxxxxxxx> > --- What happened to this patch? Because it seems like it is required for some 74kc devices to get them booting (instead of being stuck in an endless tlbmiss_handler_setup_pgd loop): * https://github.com/freifunk-gluon/gluon/issues/2784 * https://github.com/openwrt/openwrt/commit/ea6fb9c16dfb9763ea681803db65644b68bae873 * https://github.com/freifunk-gluon/gluon/pull/2810 Kind regards, Sven
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