In c0_compare_int_usable we clear compare interrupt by write value
just read out from counter to compare register.
However sometimes if those all instructions are graduated together
then it's possible that at the time compare register is written, the
counter haven't progressed, thus the interrupt is triggered again.
It also applies to QEMU that instructions is executed significantly
faster then counter.
Offset the value used to clear interrupt by one to prevent that happen.
Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx>
---
v2: Don't touch value of cnt, just offset one
---
arch/mips/kernel/cevt-r4k.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 32ec67c9ab67..368e8475870f 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -200,7 +200,7 @@ int c0_compare_int_usable(void)
*/
if (c0_compare_int_pending()) {
cnt = read_c0_count();
- write_c0_compare(cnt);
+ write_c0_compare(cnt - 1);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
if (!c0_compare_int_pending())
@@ -228,7 +228,7 @@ int c0_compare_int_usable(void)
if (!c0_compare_int_pending())
return 0;
cnt = read_c0_count();
- write_c0_compare(cnt);
+ write_c0_compare(cnt - 1);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
if (!c0_compare_int_pending())
--
2.37.1 (Apple Git-137.1)
