In c0_compare_int_usable we clear compare interrupt by write value
just read out from counter to compare register.
However sometimes if those all instructions are graduated together
then it's possible that at the time compare register is written, the
counter haven't progressed, thus the interrupt is triggered again.
It also applies to QEMU that instructions is execuated significantly
faster then counter.
Offset the counter value a litlle bit to prevent that happen.
Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx>
---
arch/mips/kernel/cevt-r4k.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 32ec67c9ab67..bbc422376e97 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -200,6 +200,8 @@ int c0_compare_int_usable(void)
*/
if (c0_compare_int_pending()) {
cnt = read_c0_count();
+ // Drawdown a little bit in case counter haven't progressed
+ cnt -= COMPARE_INT_SEEN_TICKS;
write_c0_compare(cnt);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
@@ -228,6 +230,7 @@ int c0_compare_int_usable(void)
if (!c0_compare_int_pending())
return 0;
cnt = read_c0_count();
+ cnt -= COMPARE_INT_SEEN_TICKS;
write_c0_compare(cnt);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
--
2.37.1 (Apple Git-137.1)
