Quoting Serge Semin (2022-09-29 15:53:58)
> It turns out the internal SATA reference clock signal will stay
> unavailable for the SATA interface consumer until the buffer on it's way
> is ungated. So aside with having the actual clock divider enabled we need
> to ungate a buffer placed on the signal way to the SATA controller (most
> likely some rudiment from the initial SoC release). Seeing the switch flag
> is placed in the same register as the SATA-ref clock divider at a
> non-standard ffset, let's implement it as a separate clock controller with
> the set-rate propagation to the parental clock divider wrapper. As such
> we'll be able to disable/enable and still change the original clock source
> rate.
>
> Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
>
> ---
Applied to clk-next
