Quoting Serge Semin (2022-09-29 15:53:55)
> We have discovered random glitches during the system boot up procedure.
> The problem investigation led us to the weird outcomes: when none of the
> Renesas 5P49V6901 ports are explicitly enabled by the kernel driver, the
> glitches disappeared. It was a mystery since the SoC external clock
> domains were fed with different 5P49V6901 outputs. The driver code didn't
> seem like bogus either. We almost despaired to find out a root cause when
> the solution has been found for a more modern revision of the chip. It
> turned out the 5P49V6901 clock generator stopped its output for a short
> period of time during the VC5_OUT_DIV_CONTROL register writing. The same
> problem was found for the 5P49V6965 revision of the chip and was
> successfully fixed in commit fc336ae622df ("clk: vc5: fix output disabling
> when enabling a FOD") by enabling the "bypass_sync" flag hidden inside
> "Unused Factory Reserved Register". Even though the 5P49V6901 registers
> description and programming guide doesn't provide any intel regarding that
> flag, setting it up anyway in the officially unused register completely
> eliminated the denoted glitches. Thus let's activate the functionality
> submitted in commit fc336ae622df ("clk: vc5: fix output disabling when
> enabling a FOD") for the Renesas 5P49V6901 chip too in order to remove the
> ports implicit inter-dependency.
>
> Fixes: dbf6b16f5683 ("clk: vc5: Add support for IDT VersaClock 5P49V6901")
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
> Reviewed-by: Luca Ceresoli <luca@xxxxxxxxxxxxxxxx>
>
> ---
Applied to clk-next
