Quoting Aidan MacDonald (2022-06-17 05:22:54)
> Access to registers is guarded by ingenic_tcu_{enable,disable}_regs()
> so the stop bit can be cleared before accessing a timer channel, but
> those functions did not clear the stop bit on SoCs with a global TCU
> clock gate.
>
> Testing on the X1000 has revealed that the stop bits must be cleared
> _and_ the global TCU clock must be ungated to access timer registers.
> This appears to be the norm on Ingenic SoCs, and is specified in the
> documentation for the X1000 and numerous JZ47xx SoCs.
>
> If the stop bit isn't cleared, register writes don't take effect and
> the system can be left in a broken state, eg. the watchdog timer may
> not run.
>
> The bug probably went unnoticed because stop bits are zeroed when
> the SoC is reset, and the kernel does not set them unless a timer
> gets disabled at runtime. However, it is possible that a bootloader
> or a previous kernel (if using kexec) leaves the stop bits set and
> we should not rely on them being cleared.
>
> Fixing this is easy: have ingenic_tcu_{enable,disable}_regs() always
> clear the stop bit, regardless of the presence of a global TCU gate.
>
> Reviewed-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
> Tested-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
> Fixes: 4f89e4b8f121 ("clk: ingenic: Add driver for the TCU clocks")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@xxxxxxxxx>
> ---
Applied to clk-fixes
