Re: [PATCH 1/2] MIPS: CFE: Add cfe_die()

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On 7/15/22 12:47, Florian Fainelli wrote:
> Add a cfe_die() implementation which is useful when the kernel does an
> early panic and no console is registered. This allows us to print
> useful diagnostics such as an invalid DTB having been
> configured/selected.
> 
> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> ---
>  arch/mips/fw/cfe/cfe_api.c             | 48 +++++++++++++++++++++++++-
>  arch/mips/include/asm/fw/cfe/cfe_api.h |  2 ++
>  2 files changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
> index 0c9c97ab291e..6e7883f1d47e 100644
> --- a/arch/mips/fw/cfe/cfe_api.c
> +++ b/arch/mips/fw/cfe/cfe_api.c
> @@ -13,10 +13,15 @@
>   *
>   * Authors:  Mitch Lichtenberg, Chris Demetriou
>   */
> -
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/printk.h>
> +#include <asm/mipsregs.h>
>  #include <asm/fw/cfe/cfe_api.h>
>  #include "cfe_api_int.h"
>  
> +unsigned long __initdata cfe_seal;
> +
>  /* Cast from a native pointer to a cfe_xptr_t and back.	 */
>  #define XPTR_FROM_NATIVE(n)	((cfe_xptr_t) (intptr_t) (n))
>  #define NATIVE_FROM_XPTR(x)	((void *) (intptr_t) (x))
> @@ -412,3 +417,44 @@ int cfe_writeblk(int handle, s64 offset, const char *buffer, int length)
>  		return xiocb.xiocb_status;
>  	return xiocb.plist.xiocb_buffer.buf_retlen;
>  }
> +
> +void __init cfe_die(char *fmt, ...)
> +{
> +	char msg[128];
> +	va_list ap;
> +	int handle;
> +	unsigned int count;
> +
> +	va_start(ap, fmt);
> +	vsprintf(msg, fmt, ap);
> +	strcat(msg, "\r\n");
> +
> +	if (cfe_seal != CFE_EPTSEAL)
> +		goto no_cfe;
> +
> +	/* disable XKS01 so that CFE can access the registers */
> +#if defined(CONFIG_CPU_BMIPS4380)
> +	__write_32bit_c0_register($22, 3,
> +		__read_32bit_c0_register($22, 3) & ~BIT(12));
> +#elif defined(CONFIG_CPU_BMIPS5000)
> +	__write_32bit_c0_register($22, 5,
> +		__read_32bit_c0_register($22, 5) & ~BIT(8));
> +#endif

Need to make this dynamic using read_c0_prid() because we support selecting multiple types of CPU in a single kernel image. V2 coming shortly.
-- 
Florian



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