On Sat, Jul 02, 2022 at 09:07:05PM +0200, Aleksander Jan Bajkowski wrote: > This patch is needed to handle interrupts by the second VPE on > the Lantiq xRX200, xRX300 and xRX330 SoCs. In these chips, 32 ICU > interrupts are connected to each hardware line. The SoC supports > a total of 160 interrupts. Currently changing smp_affinity to the > second VPE hangs interrupts. > > This problem affects multithreaded SoCs with a custom interrupt > controller. Chips with 1004Kc core and newer use the MIPS GIC. > > Also CC'ed Birger Koblitz and Sander Vanheule. Both are working > on support for Realtek RTL930x chips with 34Kc core and Birger > has added a patch in OpenWRT that also enables all interrupt > lines. So it looks like this patch is useful for more SoCs. > > Tested on lantiq xRX200 and xRX330. > > Signed-off-by: Aleksander Jan Bajkowski <olek2@xxxxx> > --- > arch/mips/kernel/smp-mt.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c > index 5f04a0141068..f21cd0eb1fa7 100644 > --- a/arch/mips/kernel/smp-mt.c > +++ b/arch/mips/kernel/smp-mt.c > @@ -113,8 +113,7 @@ static void vsmp_init_secondary(void) > STATUSF_IP4 | STATUSF_IP5 | > STATUSF_IP6 | STATUSF_IP7); > else > - change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | > - STATUSF_IP6 | STATUSF_IP7); > + set_c0_status(ST0_IM); > } just blindly enabling all interrupts doesn't sound like a brilliant idea even when if works on some Lantiq platforms (probably because their interrupt controller prevents issuing unwanted interrupts). But not all smp-mt platforms are Lantiq. If some CPU interrupts need to be enabled a clean interrupt controller setup with hierarchy irq domains is IMHO the correct approach, Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
