Hi,
What kernel version are you using?
Do you have the commit 1660710cf5d8 ("MIPS: mm: XBurst CPU requires
sync after DMA")?
Cheers,
-Paul
Le ven., mai 27 2022 at 19:03:56 +0800, Yunian Yang
<reimu@xxxxxxxxxxxxx> a écrit :
Hello all.
In the past month, I was struggling with random memory corruptions
and crashes on the Ingenic X1000. After some detailed testing, I need
to point out, the current cache management routines seems to be
incorrect for X1000, and maybe all X series SoCs. It mainly affects
DMA operations. Every form of peripheral to RAM transfer will corrupt
the RAM, and this includes the dwc2 and SFC's DMA and the PDMA
controller. If all the DMAs are disabled (e.g. hard coding
dma_capable = false in dwc2), it will be fine running CPU and I/O
benchmarks for a week. If you have the hardware, you can enable the
kernel data structures & memory debugging and see for yourself.
So I went back and looked at Ingenic's old 4.4 and 3.10 kernel
sources. They used a separate file (sc-xburst.c) for the cache
routines, which is based on an very old sc-mips.c. And there are two
important macros, called MIPS_CACHE_SYNC_WAR and
MIPS_BRIDGE_SYNC_WAR. They're both set to 1. However these macros are
removed from the kernel long time ago. The line
`mips_sc_ops.bc_wback_inv = mips_bridge_sync_war;' seems to be the
key point.
Do you have any recommendations of what could be done to fix this
problem?
Thanks and best regards!
