On Thu, 19 May 2022 19:51:16 +0100, Dragan Mladjenovic <Dragan.Mladjenovic@xxxxxxxxxx> wrote: > > From: Paul Burton <paulburton@xxxxxxxxxx> > > A few pieces of code in the MIPS GIC driver operate on the GIC local > register block for each online CPU, accessing each via the GIC's > other/redirect register block. This patch abstracts the process of > iterating over online CPUs & configuring the other/redirect region to > access their registers through a new gic_with_each_online_cpu() macro. > > This simplifies users of the new macro slightly, and more importantly > prepares us for handling multi-cluster systems where the register > configuration will be done via the CM's GCR_CL_REDIRECT register. By > abstracting all other/redirect block configuration through this macro, > and the __gic_with_next_online_cpu() function which backs it, users will > trivially gain support for multi-cluster when it is implemented in > __gic_with_next_online_cpu(). > > Signed-off-by: Paul Burton <paulburton@xxxxxxxxxx> > Signed-off-by: Chao-ying Fu <cfu@xxxxxxxxxxxx> > > diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c > index ff89b36267dd..4872bebe24cf 100644 > --- a/drivers/irqchip/irq-mips-gic.c > +++ b/drivers/irqchip/irq-mips-gic.c No SoB from the sender, odd patch format (no ---), and I didn't get a complete series, which makes it impossible to review things in context (I don't even know what the series is about). Please fix things and resend. M. -- Without deviation from the norm, progress is not possible.
