Remove CPU_HAS_WB from Kconfig as all Loongson64 processors don't have R3000 style write buffer. This is likely to be a legacy of Loongson 2E's Bonito64. Remove Loongson64 from war_io_reorder_wmb. Loongson64 never reorders uncached memory access as per user manual of GS464, LS3A2000 and LS3A3000. It was intruduced due to a misunderstanding of Store Fill Buffer. Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> --- arch/mips/Kconfig | 1 - arch/mips/include/asm/io.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 058446f01487..6d2e97342723 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -487,7 +487,6 @@ config MACH_LOONGSON64 select BOARD_SCACHE select CSRC_R4K select CEVT_R4K - select CPU_HAS_WB select FORCE_PCI select ISA select I8259 diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 6f5c86d2bab4..065e1ab6401a 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -219,7 +219,7 @@ void iounmap(const volatile void __iomem *addr); #define ioremap_wc(offset, size) \ ioremap_prot((offset), (size), boot_cpu_data.writecombine) -#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) +#if defined(CONFIG_CPU_CAVIUM_OCTEON) #define war_io_reorder_wmb() wmb() #else #define war_io_reorder_wmb() barrier() -- 2.35.1
