On Mon, 21 Feb 2022, Jiaxun Yang wrote: > This series clears the chaos of barrier misuse. > In prepration of light weight barrier series. What problem are you trying to solve here? The MIPS port currently implements the semantics documented in Documentation/memory-barriers.txt, in particular the "KERNEL I/O BARRIER EFFECTS" section, with extra I/O barriers borrowed from the PowerPC port for consistency for platform use, due to the weakly ordered architectural MMIO model (implementations are allowed to have a stronger model in place of course, and you are free to optimise for them with the respective configurations). Stating that we have a "chaos of barrier misuse" doesn't say anything really in my opinion and isn't particularly constructive either. This area is very fragile and you need to understand all the consequences when trying to make any changes here and show it with your submission, that is properly describe and justify your changes so that people are convinced your changes are correct and good to make. Maciej
