On Thu, Dec 16, 2021 at 01:52:04PM +0100, Thomas Bogendoerfer wrote:
> On Wed, Dec 15, 2021 at 04:44:58PM +0800, Huang Pei wrote:
> > Indexed cache operation actually uses KSEG0/CKSEG0 (AKA physical
> > address, see INDEX_BASE in arch/mips/include/asm/r4kcache.h) to
> > index cache line, so it CAN NOT handle cache alias(cache alias
> > is first introduced into MIPS by R4000, indexing cache line with
> > virtual address).
> >
> > It is said, on "32-Bit TX System TX39 Family TMPR3911/3912", P86,
> >
> > •Translation Look-aside Buffer (TLB) (4 Kbyte Page size, 32 Entries)
> > •4Kbyte instruction cache (I-cache)
> > •16 bytes (4 words) per line (256 lines total)
> > •physical address tag per cache line
> > •single valid bit per cache line
> > •direct-mapped
> > •1 Kbyte data cache (D-cache)
> > •4bytes (1 word) per line (128 lines total)
> > •physical address tag per cache line
> > •write-through
> > •two-way set associate
> >
> > We can assume there is NO cache alias on TX39's R3900 core
>
> in the same sense the whole cache flushing magic isn't needed and
> we could to the same as for pure R3k CPUs. But this code is there
> and none of the user manuals I found describe excat cache behaviour.
>
the original code is odd, I think this may be better, if we do not need
to consider cache alias
- if (cpu_has_dc_aliases || exec)
- tx39_blast_dcache_page_indexed(page);
+ tx39_blast_dcache_page_indexed(page);
if (exec)
tx39_blast_icache_page_indexed(page);
> I've planned to retire the whole tx39 soon, so please no more patches
> for it.
>
Ok, I can wait. I need more test of my patch on reviving
f685a533a7f ("MIPS: make userspace mapping young by default")
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
