Hello! On 15.12.2021 11:44, Huang Pei wrote:
Indexed cache operation actually uses KSEG0/CKSEG0 (AKA physical address, see INDEX_BASE in arch/mips/include/asm/r4kcache.h) to index cache line, so it CAN NOT handle cache alias(cache alias is first introduced into MIPS by R4000, indexing cache line with virtual address). It is said, on "32-Bit TX System TX39 Family TMPR3911/3912", P86, •Translation Look-aside Buffer (TLB) (4 Kbyte Page size, 32 Entries) •4Kbyte instruction cache (I-cache) •16 bytes (4 words) per line (256 lines total) •physical address tag per cache line •single valid bit per cache line •direct-mapped •1 Kbyte data cache (D-cache) •4bytes (1 word) per line (128 lines total) •physical address tag per cache line •write-through •two-way set associate We can assume there is NO cache alias on TX39's R3900 core Anyway, remove checking for cpu_has_dc_aliases, since tx39_*indexed can not index cache alias, nor there is cache alias on R3900 More info about TX3911/3912, see https://pdf1.alldatasheet.com/datasheet-pdf/view/211951/TOSHIBA/TMPR 3912.html Signed-off-by: Huang Pei <huangpei@xxxxxxxxxxx> --- arch/mips/mm/c-tx39.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index 03dfbb40ec73..c2ecdde0371d 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -207,11 +207,12 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page /* * Do indexed flush, too much work to get the (possible) TLB refills * to work correctly. + *
Why? [...] MBR, Sergey
