On Mon, Dec 06, 2021 at 02:19:44PM +0800, Huang Pei wrote:
> Indexed cache operation actually use KSEG0/CKSEG0 (AKA physical
> address) to index cache line, so it CAN NOT handle cache alias.
>
> Remove checking for cpu_has_dc_aliases.
>
> Signed-off-by: Huang Pei <huangpei@xxxxxxxxxxx>
> ---
> arch/mips/mm/c-tx39.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
> index 03dfbb40ec73..c2ecdde0371d 100644
> --- a/arch/mips/mm/c-tx39.c
> +++ b/arch/mips/mm/c-tx39.c
> @@ -207,11 +207,12 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
> /*
> * Do indexed flush, too much work to get the (possible) TLB refills
> * to work correctly.
> + *
> */
> - if (cpu_has_dc_aliases || exec)
> + if (exec) {
> tx39_blast_dcache_page_indexed(page);
> - if (exec)
> tx39_blast_icache_page_indexed(page);
> + }
> }
>
> static void local_tx39_flush_data_cache_page(void * addr)
do you have the hardware to test your patch or do you have at least
the manual for the CPU core used ? If both answers are no, please
drop this patch from you patch queue.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
