On Thu, Dec 2, 2021 at 8:45 PM Guenter Roeck <linux@xxxxxxxxxxxx> wrote:
>
> On 12/1/21 1:51 PM, Sergio Paracuellos wrote:
> > PCI core code call 'pcibios_root_bridge_prepare()' function inside function
> > 'pci_register_host_bridge()'. This point is very good way to properly enter
> > into this MIPS ralink specific code to properly setup I/O coherency units
> > with PCI memory addresses.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
> > ---
> > arch/mips/ralink/mt7621.c | 30 ++++++++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
> > index bd71f5b14238..7649416c1cd7 100644
> > --- a/arch/mips/ralink/mt7621.c
> > +++ b/arch/mips/ralink/mt7621.c
> > @@ -10,6 +10,7 @@
> > #include <linux/slab.h>
> > #include <linux/sys_soc.h>
> > #include <linux/memblock.h>
> > +#include <linux/pci.h>
> >
> > #include <asm/bootinfo.h>
> > #include <asm/mipsregs.h>
> > @@ -22,6 +23,35 @@
> >
> > static void *detect_magic __initdata = detect_memory_region;
> >
> > +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
> > +{
> > + struct resource_entry *entry;
> > + resource_size_t mask;
> > +
> > + entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
> > + if (!entry) {
> > + pr_err("Cannot get memory resource\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (mips_cps_numiocu(0)) {
> > + /*
> > + * FIXME: hardware doesn't accept mask values with 1s after
> > + * 0s (e.g. 0xffef), so it would be great to warn if that's
> > + * about to happen
> > + */
> > + mask = ~(entry->res->end - entry->res->start);
> > +
>
> One more comment: From the include file,
>
> #define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
>
> suggests that only the upper 16 bit are valid (relevant ?) for the mask.
> Given that, it might make sense to make sure that the lower 16 bit are not set,
> maybe with
> mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
>
Makes sense, thanks.
Best regards,
Sergio Paracuellos
> Thanks,
> Guenter
>
> > + write_gcr_reg1_base(entry->res->start);
> > + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
> > + pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
> > + (unsigned long long)read_gcr_reg1_base(),
> > + (unsigned long long)read_gcr_reg1_mask());
> > + }
> > +
> > + return 0;
> > +}
> > +
> > phys_addr_t mips_cpc_default_phys_base(void)
> > {
> > panic("Cannot detect cpc address");
> >
>
