Indexed cache operation needs KSEG0 address for safety and assumes
no dcache alias nor high memory, since indexed cache instrcution
CAN NOT handle cache alias
The TX39 core based on MIPS R3000A has 4KB Icache(direct mapped) and
1KB Dcache(2-way associate), and TX39 has no High Memory support till
now, so it is safe to use Index cache instuction with KSEG0 address
assuming no cache alias nor High Memory under 4KB page size on MIPS32
Signed-off-by: Huang Pei <huangpei@xxxxxxxxxxx>
---
arch/mips/mm/c-tx39.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 03dfbb40ec73..c7c3dbfe7756 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -170,6 +170,7 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
struct mm_struct *mm = vma->vm_mm;
pmd_t *pmdp;
pte_t *ptep;
+ unsigned long vaddr = phys_to_virt(pfn_to_phys(pfn));
/*
* If ownes no valid ASID yet, cannot possibly have gotten
@@ -207,11 +208,14 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
/*
* Do indexed flush, too much work to get the (possible) TLB refills
* to work correctly.
+ *
+ * Assuming that tx39 family do not support high memory, nor has
+ * dcache alias, vaddr can index dcache directly and correctly
*/
- if (cpu_has_dc_aliases || exec)
- tx39_blast_dcache_page_indexed(page);
- if (exec)
- tx39_blast_icache_page_indexed(page);
+ if (exec) {
+ tx39_blast_dcache_page_indexed(vaddr);
+ tx39_blast_icache_page_indexed(vaddr);
+ }
}
static void local_tx39_flush_data_cache_page(void * addr)
--
2.20.1
