Quoting Paul Cercueil (2021-05-30 09:49:19) > When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU > code expects the mux to be applied first, the divider second. > > On the JZ4760, and maybe on some other SoCs, some clocks also have a mux > setting and a divider, but the divider is not applied to all parents > selectable from the mux. > > This could be solved by creating two clocks, one with CGU_CLK_DIV and > one with CGU_CLK_MUX, but that would increase the number of clocks. > > Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit > corresponding to the parent clock's index is set, the divider is > bypassed. > > Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx> > --- Applied to clk-next
