Hello, While working on a MIPS32 BPF JIT and testing under QEMU, I've encountered some problems related to the behaviour of the SLT[I][U] opcode under MIPS ISA R6, and would appreciate some help/insight clarifying various online and documented descriptions. In "Introduction to the MIPS32 Architecture" (MD00082-2B-MIPS32INT-AFP-06.01), some wording states: "CPU truth values ... are replaced by Release 6 instructions that generate truth values of all zeroes or all ones (suitable for logical operations involving masks) and interpret all zeroes or any non-zero bit as true or false ..." This change is also echoed elsewhere online: - https://www.linuxsecrets.com/linux-mips-wiki/MIPS_Release_6.html#MIPS32.2F64_Release_6 - https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64 However, in "The MIPS32® Instruction Set Manual" (MD00086-2B-MIPS32BIS-AFP-6.06), the SLTU insn *is not* specified to generate all-ones truth values. Generating all-ones truth values for SLTU impacts things like carry-addition code written for MIPS32R6, such as in my BPF JIT R6-support code. Curiously, while testing this under QEMU I saw many test-case failures, and debugging seemed to show QEMU not generating all-ones truth values when emulating the R6 ISA. Thus, the key questions: 1. What is the correct/expected output of SLT under the MIPS ISA R6? 2. Does QEMU properly emulate SLT under ISA R6? If not, how do other developers reliably test for R6 compliance? Thanks in advance for any help, Tony
