> Am 22.04.2021 um 18:55 schrieb Maciej W. Rozycki <macro@xxxxxxxxxxx>: > > > Have you used it as a module or at bootstrap? I did load it by insmod. > I would expect your JZ4730 device to have the CP0 Count register as well, > as it has been architectural ever since MIPS III really, or is your system > SMP with CP0 Count registers out of sync across CPUs due to sleep modes or > whatever? It switches clocksource to some operating system timers on the SoC which may have an influence on the resolution (or precision). > Thanks for sharing your figures. It was a pleasure towards better MIPS support... > >> [1] we are preparing full support for the JZ4730 based Skytone Alpha machine. Most features >> are working except sound/I2S. I2C is a little unreliable and Ethernet has hickups. And scheduling >> which indicates some fundamental IRQ or timer issue we could not yet identify. > > Good luck with that! BR and thanks, Niklaus
