Most MT7621 SoCs have 2 cores, which is detected and supported properly by CPS. Unfortunately, MT7621 SoC has a less common S variant with only one core. On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when starting SMP. CPULAUNCH registers can be used in that case to detect the absence of the second core and override the GCR_CONFIG PCORES field. Rework a long-standing OpenWrt patch to override the value of mips_cps_numcores on single-core MT7621 systems. Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core MT7621 device (Netgear R6220). Original 4.14 OpenWrt patch: Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7 Current 5.10 OpenWrt patch: Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904 Suggested-by: Felix Fietkau <nbd@xxxxxxxx> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@xxxxxxxxx> --- arch/mips/include/asm/bugs.h | 18 ++++++++++++++++++ arch/mips/kernel/smp-cps.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index d72dc6e1cf3c..d32f0c4e61f7 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -16,6 +16,7 @@ #include <asm/cpu.h> #include <asm/cpu-info.h> +#include <asm/mips-boards/launch.h> extern int daddiu_bug; @@ -50,4 +51,21 @@ static inline int r4k_daddiu_bug(void) return daddiu_bug != 0; } +static inline void cm_gcr_pcores_bug(unsigned int *ncores) +{ + struct cpulaunch *launch; + + if (!IS_ENABLED(CONFIG_SOC_MT7621) || !ncores) + return; + + /* + * Ralink MT7621S SoC is single core, but GCR_CONFIG always reports 2 cores. + * Use legacy amon method to detect if the second core is missing. + */ + launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + launch += 2; /* MT7621 has 2 VPEs per core */ + if (!(launch->flags & LAUNCH_FREADY)) + *ncores = 1; +} + #endif /* _ASM_BUGS_H */ diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index bcd6a944b839..e1e9c11e8a7c 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -15,6 +15,7 @@ #include <linux/irq.h> #include <asm/bcache.h> +#include <asm/bugs.h> #include <asm/mips-cps.h> #include <asm/mips_mt.h> #include <asm/mipsregs.h> @@ -60,6 +61,7 @@ static void __init cps_smp_setup(void) pr_cont("{"); ncores = mips_cps_numcores(cl); + cm_gcr_pcores_bug(&ncores); for (c = 0; c < ncores; c++) { core_vpes = core_vpe_count(cl, c); @@ -170,6 +172,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); + cm_gcr_pcores_bug(&ncores); mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), GFP_KERNEL); if (!mips_cps_core_bootcfg) { -- 2.31.1
