On 02/09/2021 10:36 AM, Jiaxun Yang wrote:
On Tue, Feb 9, 2021, at 12:32 AM, Jiaxun Yang wrote:
On Mon, Feb 8, 2021, at 9:14 PM, Tiezhu Yang wrote:
According to MIPS EJTAG Specification [1], a Debug Breakpoint
exception occurs when an SDBBP instruction is executed, the
CP0_DEBUG bit DBp indicates that a Debug Breakpoint exception
occurred, just check bit DBp for SDBBP is more accurate.
[1] http://www.t-es-t.hu/download/mips/md00047f.pdf
Signed-off-by: Tiezhu Yang <yangtiezhu@xxxxxxxxxxx>
---
arch/mips/kernel/genex.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index bcce32a..6336826 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -349,8 +349,8 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp)
MTC0 k0, CP0_DESAVE
mfc0 k0, CP0_DEBUG
- sll k0, k0, 30 # Check for SDBBP.
- bgez k0, ejtag_return
+ andi k0, k0, 0x2 # Check for SDBBP.
+ beqz k0, ejtag_return
You'd better define a marco for it to prevent further confusion.
OK, thanks, I will do it in v2.
Btw I'm curious about how do kernel receive EJTAG exception?
In my understanding there are only two possible EJTAG exception vectors,
0xbfc00480 and DSEG one. Both of them are reachable by kernel.
^ not
How do this piece of code work?
We can see some useful explanations from the following comment,
the firmware needs to make sure jump to except_vec_ejtag_debug.
arch/mips/kernel/genex.S
/*
* EJTAG debug exception handler.
* The EJTAG debug exception entry point is 0xbfc00480, which
* normally is in the boot PROM, so the boot PROM must do an
* unconditional jump to this vector.
*/
NESTED(except_vec_ejtag_debug, 0, sp)
j ejtag_debug_handler
#ifdef CONFIG_CPU_MICROMIPS
nop
#endif
END(except_vec_ejtag_debug)
Thanks.
- Jiaxun
#ifdef CONFIG_SMP
1: PTR_LA k0, ejtag_debug_buffer_spinlock
--
2.1.0
--
- Jiaxun
