From: Jia Qingtong <jiaqingtong97@xxxxxxx> Some Cavium Octeon CPUs(Octeon & Octeon Plus) suffer from a bug that causes a single wmb ordering barrier to be ineffective, requiring the use of 2 in sequence to provide an effective barrier. This patch make workaroud as a config for CPUs who didn't suffer from that bug. Signed-off-by: Jia Qingtong <jiaqingtong97@xxxxxxx> --- arch/mips/cavium-octeon/Kconfig | 9 +++++++++ arch/mips/include/asm/sync.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 4984e462be30..0dc910683df9 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -1,6 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 if CPU_CAVIUM_OCTEON +config WAR_OCTEON_BARRIER + bool "Enable Octeon & Octeon Plus barrier workaround" + default "y" + help + Some Cavium Octeon CPUs(Octeon & Octeon Plus) + suffer from a bug that causes a single wmb ordering barrier + to be ineffective, requiring the use of 2 in sequence + to provide an effective barrier. + config CAVIUM_CN63XXP1 bool "Enable CN63XXP1 errata workarounds" default "n" diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h index aabd097933fe..b24a2f82ef19 100644 --- a/arch/mips/include/asm/sync.h +++ b/arch/mips/include/asm/sync.h @@ -158,7 +158,7 @@ * Note that this expression is evaluated by the assembler (not the compiler), * and that the assembler evaluates '==' as 0 or -1, not 0 or 1. */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON +#ifdef CONFIG_WAR_OCTEON_BARRIER # define __SYNC_rpt(type) (1 - (type == __SYNC_wmb)) #else # define __SYNC_rpt(type) 1 -- 2.28.0
