On Tue, Sep 22, 2020 at 10:06:24AM +0800, Huacai Chen wrote:
> On Mon, Aug 24, 2020 at 3:40 PM Huacai Chen <chenhc@xxxxxxxxxx> wrote:
> >
> > If MSA is enabled, FPU_REG_WIDTH is 128 rather than 64, then get_fpr64()
> > /set_fpr64() in the original unaligned instruction emulation code access
> > the wrong fp registers. This is because the current code doesn't specify
> > the correct index field, so fix it.
> >
> > Fixes: f83e4f9896eff614d0f2547a ("MIPS: Loongson-3: Add some unaligned instructions emulation")
> > Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx>
> > Signed-off-by: Pei Huang <huangpei@xxxxxxxxxxx>
> > ---
> > arch/mips/loongson64/cop2-ex.c | 24 ++++++++----------------
> > 1 file changed, 8 insertions(+), 16 deletions(-)
should this go via mips-fixes ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
