On Tue, Aug 25, 2020 at 01:05:31PM +0300, Sergei Shtylyov wrote:
OK, got it, anything else?
>From 0f4003eb418737df75cb8be79d4da34b1500f3d7 Mon Sep 17 00:00:00 2001
From: Huang Pei <huangpei@xxxxxxxxxxx>
Date: Fri, 21 Aug 2020 10:48:40 +0800
Subject: [PATCH] MIPS: add missing MSACSR and upper MSA initialization
init_fp_ctx just initialize the fp/msa context, and own_fp_inatomic
just restore FCSR and 64bit FP regs from it, but miss MSACSR and upper
MSA regs for MSA, so MSACSR and MSA upper regs's value from previous
task on current cpu can leak into current task and cause unpredictable
behavior when MSA context not initialized.
Signed-off-by: Huang Pei <huangpei@xxxxxxxxxxx>
---
arch/mips/kernel/traps.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 38aa07ccdbcc..e843b38486b8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1287,6 +1287,16 @@ static int enable_restore_fp_context(int msa)
err = own_fpu_inatomic(1);
if (msa && !err) {
enable_msa();
+ /* with MSA enabled, userspace can see MSACSR
+ * and MSA regs, but the values in them are from
+ * other task before current task, restore them
+ * from saved fp/msa context
+ */
+ write_msa_csr(current->thread.fpu.msacsr);
+ /* own_fpu_inatomic(1) just restore low 64bit,
+ * fix the high 64bit
+ */
+ init_msa_upper();
set_thread_flag(TIF_USEDMSA);
set_thread_flag(TIF_MSA_CTX_LIVE);
}
--
2.17.1
> Hello!
>
> On 25.08.2020 7:38, Huang Pei wrote:
>
> > init_fp_ctx just initialize the fp/msa context, and own_fp_inatomic
> > just restore FCSR and 64bit FP regs from it, but miss MSACSR and upper
> > MSA regs for MSA, so MSACSR and MSA upper regs's value from previous
> > task on current cpu can leak into current task and cause unpredictable
> > behavior when MSA context not initialized.
> >
> > Signed-off-by: Huang Pei <huangpei@xxxxxxxxxxx>
> > ---
> > arch/mips/kernel/traps.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> > index 38aa07ccdbcc..f8334b63e4c8 100644
> > --- a/arch/mips/kernel/traps.c
> > +++ b/arch/mips/kernel/traps.c
> > @@ -1287,6 +1287,14 @@ static int enable_restore_fp_context(int msa)
> > err = own_fpu_inatomic(1);
> > if (msa && !err) {
> > enable_msa();
> > + /* with MSA enabled, userspace can see MSACSR
> > + * and MSA regs, but the values in them are from
> > + * other task before current task, restore them
> > + * from saved fp/msa context */
> > + write_msa_csr(current->thread.fpu.msacsr);
> > + /* own_fpu_inatomic(1) just restore low 64bit,
> > + * fix the high 64bit */
>
> The preferred multi-line comment style is:
>
> /*
> * bla
> * bla
> */
>
> > + init_msa_upper();
> > set_thread_flag(TIF_USEDMSA);
> > set_thread_flag(TIF_MSA_CTX_LIVE);
> > }
>
> MBR, Sergei
