Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel mode by default. However, gslq/gssq (16-bytes load/store instructions) overrides the instruction format of lwc2/swc2. If we wan't to use gslq/ gssq for optimization in kernel, we should enable COP2 usage in kernel. Please pay attention that in this patch we only enable COP2 in kernel, which means it will lose ST0_CU2 when a process go to user space (try to use COP2 in user space will trigger an exception and then grab COP2, which is similar to FPU). And as a result, we need to modify the context switching code because the new scheduled process doesn't contain ST0_CU2 in its THERAD_STATUS probably. Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx> --- V3: Stop using ST0_MM and use ST0_CU2 instead (Thank Thomas and Maciej). V4: Adopt Thomas's suggestion to improve coding style. arch/mips/boot/compressed/head.S | 7 +++++++ arch/mips/include/asm/mipsregs.h | 7 +++++++ arch/mips/include/asm/stackframe.h | 6 +++--- arch/mips/kernel/head.S | 2 +- arch/mips/kernel/process.c | 2 +- arch/mips/kernel/r4k_switch.S | 3 +++ arch/mips/kernel/traps.c | 2 +- 7 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S index 409cb48..4580316 100644 --- a/arch/mips/boot/compressed/head.S +++ b/arch/mips/boot/compressed/head.S @@ -14,11 +14,18 @@ #include <asm/asm.h> #include <asm/regdef.h> +#include <asm/mipsregs.h> .set noreorder .cprestore LEAF(start) start: +#ifdef CONFIG_CPU_LOONGSON64 + mfc0 t0, CP0_STATUS + or t0, ST0_CU2 /* make 16-bytes load/store instructions usable */ + mtc0 t0, CP0_STATUS +#endif + /* Save boot rom start args */ move s0, a0 move s1, a1 diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 4ddc12e..cc93e3f 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -389,6 +389,13 @@ #define ST0_CU3 0x80000000 #define ST0_XX 0x80000000 /* MIPS IV naming */ +/* in-kernel enabled CUs */ +#ifdef CONFIG_CPU_LOONGSOON64 +#define ST0_KERNEL_CUMASK (ST0_CU0 | ST_CU2) +#else +#define ST0_KERNEL_CUMASK ST0_CU0 +#endif + /* * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) */ diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 3e8d2aa..aa430a6 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -450,7 +450,7 @@ */ .macro CLI mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | STATMASK + li t1, ST0_KERNEL_CUMASK | STATMASK or t0, t1 xori t0, STATMASK mtc0 t0, CP0_STATUS @@ -463,7 +463,7 @@ */ .macro STI mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | STATMASK + li t1, ST0_KERNEL_CUMASK | STATMASK or t0, t1 xori t0, STATMASK & ~1 mtc0 t0, CP0_STATUS @@ -477,7 +477,7 @@ */ .macro KMODE mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | (STATMASK & ~1) + li t1, ST0_KERNEL_CUMASK | (STATMASK & ~1) #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) andi t2, t0, ST0_IEP srl t2, 2 diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 7dd234e..61b7358 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -35,7 +35,7 @@ .macro setup_c0_status set clr .set push mfc0 t0, CP0_STATUS - or t0, ST0_CU0|\set|0x1f|\clr + or t0, ST0_KERNEL_CUMASK|\set|0x1f|\clr xor t0, 0x1f|\clr mtc0 t0, CP0_STATUS .set noreorder diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index f5dc316..9412314 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -68,7 +68,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) unsigned long status; /* New thread loses kernel privileges. */ - status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); + status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK); status |= KU_USER; regs->cp0_status = status; lose_fpu(0); diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 58232ae..c2fde40 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -53,6 +53,9 @@ nor a3, $0, a3 and a2, a3 or a2, t1 +#ifdef CONFIG_CPU_LOONGSON64 + or a2, ST0_CU2 /* make 16-bytes load/store instructions usable */ +#endif mtc0 a2, CP0_STATUS move v0, a0 jr ra diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 38aa07c..14225b6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2192,7 +2192,7 @@ static void configure_status(void) * flag that some firmware may have left set and the TS bit (for * IP27). Set XX for ISA IV code to work. */ - unsigned int status_set = ST0_CU0; + unsigned int status_set = ST0_KERNEL_CUMASK; #ifdef CONFIG_64BIT status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; #endif -- 2.7.0
