在 2020/8/7 21:13, Thomas Bogendoerfer 写道:
On Wed, Aug 05, 2020 at 09:51:44PM +0800, Jiaxun Yang wrote:
yes there is. Since this COP2 is a total black box to me, it would be
really helpfull to get some docs for it or at least some information what
it exactly does and how you want to use it in kernel code.
FYI:
Loongson doesn't have any CU2 register. It just reused LWC2 & LDC2 opcode
to define some load & store instructions (e.g. 128bit load to two GPRs).
I have a collection of these instructions here[1].
From GS464E (3A2000+), execuating these instruction won't produce COP2
unusable
exception. But older Loongson cores (GS464) will still produce COP2
exception, thus
we should have CU2 enabled in kernel. That would allow us use to these
instructions
to optimize kernel.
thank you that makes things a little bit clearer.
How will this be used in kernel code ? Special assembler routines or
by enabling gcc options ?
Via special assembly routines, as -msoft-float will disable generation of
these instructions in GCC.
I knew Huacai have out-of-tree memcpy optimization and Xuerui have
RAID5 optimiztion with these instructions.
And finally what I stil don't like is the splittering of more
#ifdef LOONGSON into common code. I'd prefer a more generic way
to enable COPx for in kernel usage. Maybe a more generic config option
or a dynamic solution like the one for user land.
Agreed. some Kconfig options or cpuinfo_mips.options can be helpful.
let's see whether this really is needed.
To me it looks like the COP2 exception support for loongson makes
thing worse than it helps. How about the patch below ? There is still
a gap between starting the kernel and COP2 enabled for which I'm not
sure, if we are hitting COP2 instructions.
Yes, the exception does not really make sense.
What's your opinion Huacai?
For in-kernel usage, we still have to enable it in genex.
Thanks for your advice~
- Jiaxun
Thomas.
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 6b7396a6a115..dfa72e9be64a 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -33,13 +33,6 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
#define cop2_present 1
#define cop2_lazy_restore 0
-#elif defined(CONFIG_CPU_LOONGSON64)
-
-#define cop2_present 1
-#define cop2_lazy_restore 1
-#define cop2_save(r) do { (void)(r); } while (0)
-#define cop2_restore(r) do { (void)(r); } while (0)
-
#else
#define cop2_present 0
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b95ef98fc847..f0a8ef5a8605 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2194,6 +2194,11 @@ static void configure_status(void)
#ifdef CONFIG_64BIT
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
#endif
+#ifdef CONFIG_CPU_LOONGSON64
+ /* enable 16-bytes load/store instructions */
+ status_set |= ST0_CU2;
+#endif
+
if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
status_set |= ST0_XX;
if (cpu_has_dsp)
