On 01/14/2016 04:14 AM, Will Deacon wrote:
On Wed, Jan 13, 2016 at 02:26:16PM -0800, Leonid Yegoshin wrote:
Moreover, there are voices against guarantee that it will be in future
and that voices point me to Documentation/memory-barriers.txt section "DATA
DEPENDENCY BARRIERS" examples which require SYNC_RMB between loading
address/index and using that for loading data based on that address or index
for shared data (look on CPU2 pseudo-code):
To deal with this, a data dependency barrier or better must be inserted
between the address load and the data load:
CPU 1 CPU 2
=============== ===============
{ A == 1, B == 2, C = 3, P == &A, Q == &C }
B = 4;
<write barrier>
WRITE_ONCE(P, &B);
Q = READ_ONCE(P);
<data dependency barrier> <-----------
SYNC_RMB is here
D = *Q;
...
Another example of where data dependency barriers might be required is
where a
number is read from memory and then used to calculate the index for an
array
access:
CPU 1 CPU 2
=============== ===============
{ M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
M[1] = 4;
<write barrier>
WRITE_ONCE(P, 1);
Q = READ_ONCE(P);
<data dependency barrier> <------------
SYNC_RMB is here
D = M[Q];
That voices say that there is a legitimate reason to relax HW here for
performance if SYNC_RMB is needed anyway to work with this sequence of
shared data.
Are you saying that MIPS needs to implement [smp_]read_barrier_depends?
It is not me, it is Documentation/memory-barriers.txt from kernel sources.
HW team can't work on voice statements, it should do a work on written
documents. If that is written (see above the lines which I marked by
"SYNC_RMB") then anybody should use it and never mind how many
CPUs/Threads are in play. This examples explicitly requires to insert
"data dependency barrier" between reading a shared pointer/index and
using it to fetch a shared data. So, your WRC+addr+addr test is a
violation of that recommendation.
- Leonid.
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