On 01/13/2016 02:45 AM, Will Deacon wrote:
On Tue, Jan 12, 2016 at 12:45:14PM -0800, Leonid Yegoshin wrote:
I don't think the address dependency is enough on its own. By that
reasoning, the following variant (WRC+addr+addr) would work too:
P0:
Wx = 1
P1:
Rx == 1
<address dep>
Wy = 1
P2:
Ry == 1
<address dep>
Rx = 0
So are you saying that this is also forbidden?
Imagine that P0 and P1 are two threads that share a store buffer. What
then?
I ask HW team about it but I have a question - has it any relationship
with replacing MIPS SYNC with lightweight SYNCs (SYNC_WMB etc)? You use
any barrier or do not use it and I just voice an intention to use a more
efficient instruction instead of bold hummer (SYNC instruction). If you
don't use any barrier here then it is a different issue.
May be it has sense to return back to original issue?
- Leonid
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