On Wed, Aug 12, 2015 at 10:00 AM, James Bottomley <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx> wrote: > On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote: ... >> However the ccio (parisc) and sba_iommu (parisc & ia64) IOMMUs seem >> to be operate mostly on virtual addresses. It's a fairly odd concept >> that I don't fully grasp, so I'll need some help with those if we want >> to bring this forward. James explained the primary function of IOMMUs on parisc (DMA-Cache coherency) much better than I ever could. Three more observations: 1) the IOMMU can be bypassed by 64-bit DMA devices on IA64. 2) IOMMU enables 32-bit DMA devices to reach > 32-bit physical memory and thus avoiding bounce buffers. parisc and older IA-64 have some 32-bit PCI devices - e.g. IDE boot HDD. 3) IOMMU acts as a proxy for IO devices by fetching cachelines of data for PA-RISC systems whose memory controllers ONLY serve cacheline sized transactions. ie. 32-bit DMA results in the IOMMU fetching the cacheline and updating just the 32-bits in a DMA cache coherent fashion. Bonus thought: 4) IOMMU can improve DMA performance in some cases using "hints" provided by the OS (e.g. prefetching DMA data or using READ_CURRENT bus transactions instead of normal memory fetches.) cheers, grant -- To unsubscribe from this list: send the line "unsubscribe linux-metag" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
