On 14/11/13 11:33, Xishi Qiu wrote:
> On 2013/11/14 18:24, James Hogan wrote:
>
>> On 14/11/13 09:35, Chen Gang wrote:
>>> On 11/14/2013 05:18 PM, James Hogan wrote:
>>>> On Thursday 14 November 2013 16:11:21 Chen Gang wrote:
>>>>> Like another p?d_alloc(), pud_alloc() also may fail, so need check it.
>>>>>
>>>>> Signed-off-by: Chen Gang <gang.chen@xxxxxxxxxxx>
>>>>
>>>> NAK.
>>>>
>>>> pud_alloc folds to pud_offset on Meta so it cannot fail.
>>>>
>>>
>>> If so, can pmd_alloc() be fail?
>>
>> No. pmd_alloc folds to pmd_offset so it also cannot fail, and the
>> existing !pmd check is dead code. The following would be better.
>>
>> Cheers
>> James
>>
>> >From 85a386a9c7df666b1f438435be8a89581bc7e8b3 Mon Sep 17 00:00:00 2001
>> From: James Hogan <james.hogan@xxxxxxxxxx>
>> Date: Thu, 14 Nov 2013 10:14:37 +0000
>> Subject: [PATCH 1/1] metag: dma: remove dead code in dma_alloc_init()
>>
>> Meta has 2 levels of page table so the pmd folds into the pud which
>
> Hi James,
>
> "Meta has 2 levels of page table", so it use
> "#define pud_alloc(mm, pgd, address) (pgd)", right?
Essentially yes. It uses the definitions in include/linux/mm.h:
> static inline pud_t *pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address)
> {
> return (unlikely(pgd_none(*pgd)) && __pud_alloc(mm, pgd, address))?
> NULL: pud_offset(pgd, address);
> }
>
> static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address)
> {
> return (unlikely(pud_none(*pud)) && __pmd_alloc(mm, pud, address))?
> NULL: pmd_offset(pud, address);
> }
arch/metag/include/asm/pgtable.h includes asm-generic/pgtable-nopmd.h
which includes asm-generic/pgtable-nopud.h, so:
pgd_none() is always 0
__pud_alloc() is always 0
pud_alloc() = pud_offset() = pgd
pud_none() is always 0
__pmd_alloc() is always 0
pmd_alloc() = pmd_offset() = pud
> and if the arch is x86_64, we should check the pmd and pud, right?
I believe x86_64 uses 4 level page tables so yes, but you're probably
best off checking the relevant definitions, disassembling some code, or
asking the x86 maintainers. I believe there's been an article or two
about 4 level page tables on LWN too.
Cheers
James
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