At least on NVT6779D clearing the wake fifo works in learning mode only
(although this condition is not mentioned in the chip spec).
Setting the clear fifo bit has no effect in wake up mode.
Even if clearing the wake fifo should work in wake up mode on other
chips this workaround doesn't hurt.
If needed the caller of nvt_clear_cir_wake_fifo has to take care
of locking.
Signed-off-by: Heiner Kallweit <hkallweit1@xxxxxxxxx>
---
drivers/media/rc/nuvoton-cir.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/media/rc/nuvoton-cir.c b/drivers/media/rc/nuvoton-cir.c
index 8ed8011..f624851 100644
--- a/drivers/media/rc/nuvoton-cir.c
+++ b/drivers/media/rc/nuvoton-cir.c
@@ -379,11 +379,19 @@ static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
/* clear out the hardware's cir wake rx fifo */
static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
{
- u8 val;
+ u8 val, config;
+
+ config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
+
+ /* clearing wake fifo works in learning mode only */
+ nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
+ CIR_WAKE_IRCON);
val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
CIR_WAKE_FIFOCON);
+
+ nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
}
/* clear out the hardware's cir tx fifo */
--
2.6.4
--
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