On Mon, Sep 21, 2015 at 11:55:53AM -0700, Bryan Wu wrote:
[...]
> +static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable)
> +{
> + struct tegra_csi_device *csi = to_csi(subdev);
> + struct tegra_channel *chan = subdev->host_priv;
> + enum tegra_csi_port_num port_num = (chan->port & 1) ? PORT_B : PORT_A;
> + struct tegra_csi_port *port = &csi->ports[port_num];
> + int ret;
> +
> + if (enable) {
[...]
> + } else {
> + u32 val = pp_read(port, TEGRA_CSI_PIXEL_PARSER_STATUS);
> + dev_dbg(csi->dev, "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n", val);
> +
> + val = cil_read(port, TEGRA_CSI_CIL_STATUS);
> + dev_dbg(csi->dev, "TEGRA_CSI_CIL_STATUS 0x%08x\n", val);
> +
> + val = cil_read(port, TEGRA_CSI_CILX_STATUS);
> + dev_dbg(csi->dev, "TEGRA_CSI_CILX_STATUS 0x%08x\n", val);
> +
I was going to apply this and give it a spin, but then git am complained
about trailing whitespace above...
> +#ifdef DEBUG
> + val = csi_read(csi, TEGRA_CSI_DEBUG_COUNTER_0);
> + dev_err(&csi->dev, "TEGRA_CSI_DEBUG_COUNTER_0 0x%08x\n", val);
> +#endif
> +
> + pp_write(port, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
> + (0xF << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
> + CSI_PP_DISABLE);
> +
> + clk_disable_unprepare(csi->clk);
> + }
> +
and here, ...
> +static int tegra_csi_probe(struct platform_device *pdev)
> +{
[...]
> + for (i = 0; i < TEGRA_CSI_PORTS_NUM; i++) {
> + /* Initialize the default format */
> + csi->ports[i].format.code = TEGRA_VF_DEF;
> + csi->ports[i].format.field = V4L2_FIELD_NONE;
> + csi->ports[i].format.colorspace = V4L2_COLORSPACE_SRGB;
> + csi->ports[i].format.width = TEGRA_DEF_WIDTH;
> + csi->ports[i].format.height = TEGRA_DEF_HEIGHT;
> +
> + /* Initialize port register bases */
> + csi->ports[i].pixel_parser = csi->iomem +
> + (i & 1) * TEGRA_CSI_PORT_OFFSET;
> + csi->ports[i].cil = csi->iomem + TEGRA_CSI_CIL_OFFSET +
here and...
> + (i & 1) * TEGRA_CSI_PORT_OFFSET;
> + csi->ports[i].tpg = csi->iomem + TEGRA_CSI_TPG_OFFSET +
here.
Might be worth fixing those up if you'll respin anyway.
Thierry
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