On Wed, Jan 28, 2015 at 05:55:06PM +0100, Philipp Zabel wrote: > + <para>On LVDS buses, usually each sample is transferred serialized in > + seven time slots per pixel clock, on three (18-bit) or four (24-bit) > + differential data pairs at the same time. The remaining bits are used for > + control signals as defined by SPWG/PSWG/VESA or JEIDA standards. > + The 24-bit RGB format serialized in seven time slots on four lanes using > + JEIDA defined bit mapping will be named > + <constant>MEDIA_BUS_FMT_RGB888_1X7X3_JEIDA</constant>, for example. > + </para> Hi Philipp, Should that example be MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA instead of 1X7X3? Regards, Steve -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
