The hack I put in a couple of years ago to avoid clock stretching issues
when talking to the xc5000 worked fine for writes, but intermittently fails
for register reads, because the xc5000 may stretch the clock for longer
between bytes (I was seeing cases of 21 us on the analyzer).
The problem manifested itself as the xc5000 firmware version and PLL lock
register intermittently showing garbage values.
Slow down the i2c bus from 30 KHz to 20 KHz to accommodate.
Signed-off-by: Devin Heitmueller <dheitmueller@xxxxxxxxxxxxxx>
---
drivers/media/video/au0828/au0828-cards.c | 4 ++--
drivers/media/video/au0828/au0828-reg.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/media/video/au0828/au0828-cards.c b/drivers/media/video/au0828/au0828-cards.c
index 1c6015a..4a09b0e 100644
--- a/drivers/media/video/au0828/au0828-cards.c
+++ b/drivers/media/video/au0828/au0828-cards.c
@@ -46,7 +46,7 @@ struct au0828_board au0828_boards[] = {
.name = "Hauppauge HVR850",
.tuner_type = TUNER_XC5000,
.tuner_addr = 0x61,
- .i2c_clk_divider = AU0828_I2C_CLK_30KHZ,
+ .i2c_clk_divider = AU0828_I2C_CLK_20KHZ,
.input = {
{
.type = AU0828_VMUX_TELEVISION,
@@ -77,7 +77,7 @@ struct au0828_board au0828_boards[] = {
stretch fits inside of a normal clock cycle, or else the
au0828 fails to set the STOP bit. A 30 KHz clock puts the
clock pulse width at 18us */
- .i2c_clk_divider = AU0828_I2C_CLK_30KHZ,
+ .i2c_clk_divider = AU0828_I2C_CLK_20KHZ,
.input = {
{
.type = AU0828_VMUX_TELEVISION,
diff --git a/drivers/media/video/au0828/au0828-reg.h b/drivers/media/video/au0828/au0828-reg.h
index c39f3d2..2140f4c 100644
--- a/drivers/media/video/au0828/au0828-reg.h
+++ b/drivers/media/video/au0828/au0828-reg.h
@@ -63,3 +63,4 @@
#define AU0828_I2C_CLK_250KHZ 0x07
#define AU0828_I2C_CLK_100KHZ 0x14
#define AU0828_I2C_CLK_30KHZ 0x40
+#define AU0828_I2C_CLK_20KHZ 0x60
--
1.7.1
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