On Wed, Aug 03, 2011 at 12:43:50PM -0500, James Bottomley wrote: > I assume from the above that ARM has a hardware page walker? Correct, and speculative prefetch (which isn't prevented by not having TLB entries), so you can't keep entries out of the TLB. If it's in the page tables it can end up in the TLB. The problem is that we could end up with conflicting attributes available to the hardware for the same physical page, and it is _completely_ undefined how hardware behaves with that (except that it does not halt - and there's no exception path for the condition because there's no detection of the problem case.) So, if you had one mapping which was fully cacheable and another mapping which wasn't, you can flush the TLB all you like - it could be possible that you still up with an access through the non-cacheable mapping being cached (either hitting speculatively prefetched cache lines via the cacheable mapping, or the cacheable attributes being applied to the non-cacheable mapping - or conversely uncacheable attributes applied to the cacheable mapping.) Essentially, the condition is labelled 'unpredictable' in the TRMs, which basically means that not even observed behaviour can be relied upon, because there may be cases where the observed behaviour fails. -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
