Hi Jacopo,
Thank you for the patch.
On Fri, Mar 21, 2025 at 04:45:39PM +0100, Jacopo Mondi wrote:
> Add formats definition for RAW Bayer formats in vsp1_pipe.c.
>
> 8-bits RAW Bayer pixel formats map on VSP format RGB332.
s/map on/map to/
> 10, 12 and 16 bits RAW Bayer pixel formats map on RGB565 insted.
>
> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@xxxxxxxxxxxxxxxx>
> ---
> v3->v4:
> - Fix SWAP bits for RAW 10, 12 and 16
> ---
> drivers/media/platform/renesas/vsp1/vsp1_pipe.c | 72 ++++++++++++++++++++++++-
> 1 file changed, 71 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_pipe.c b/drivers/media/platform/renesas/vsp1/vsp1_pipe.c
> index 8e9be3ec1b4d..a51061738edc 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_pipe.c
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_pipe.c
> @@ -30,10 +30,80 @@
> */
>
> static const struct vsp1_format_info vsp1_video_formats[] = {
> - { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
> + /* Raw Bayer 8-bit: Maps on RGB332 */
> + { V4L2_PIX_FMT_SBGGR8, MEDIA_BUS_FMT_Y8_1X8,
> + VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
> + 1, { 8, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SGBRG8, MEDIA_BUS_FMT_Y8_1X8,
> + VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
> + 1, { 8, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SGRBG8, MEDIA_BUS_FMT_Y8_1X8,
> + VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
> + 1, { 8, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SRGGB8, MEDIA_BUS_FMT_Y8_1X8,
> VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
> 1, { 8, 0, 0 }, false, false, 1, 1, false },
Similarly to the media bus codes, could we have a single entry, using
V4L2_PIX_FMT_GREY ? Same below with V4L2_PIX_FMT_Y10, V4L2_PIX_FMT_Y12
and V4L2_PIX_FMT_Y16.
This would still duplicate entries, as V4L2_PIX_FMT_Y1[026] are
essentially treated the same, and they are identical to
V4L2_PIX_FMT_RGB565. We could ask the ISP driver to use
V4L2_PIX_FMT_RGB565 (and V4L2_PIX_FMT_RGB332 for 8-bit raw) when
configuring the VSPX, but that's a bit of a hack.
Another option would be to handle the translation in
vsp1_vspx_rwpf_set_subdev_fmt(). I would still in that case only expect
the V4L2_PIX_FMT_GREY and V4L2_PIX_FMT_Y* 4CCs from the ISP driver. This
patch could then be dropped.
What's your preference ?
> +
> + /* Raw Bayer 10/12/16-bit: Maps on RGB565 */
> + { V4L2_PIX_FMT_SBGGR10, MEDIA_BUS_FMT_Y10_1X10,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 10, 0, 0 }, false, false, 1, 1, false },
The bpp values are used to calculate memory offsets. Unless I'm
mistaken, you should use 16 here, not 10.
> + { V4L2_PIX_FMT_SGBRG10, MEDIA_BUS_FMT_Y10_1X10,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 10, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SGRBG10, MEDIA_BUS_FMT_Y10_1X10,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 10, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SRGGB10, MEDIA_BUS_FMT_Y10_1X10,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 10, 0, 0 }, false, false, 1, 1, false },
> +
> + { V4L2_PIX_FMT_SBGGR12, MEDIA_BUS_FMT_Y12_1X12,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 12, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SGBRG12, MEDIA_BUS_FMT_Y12_1X12,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 12, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SGRBG12, MEDIA_BUS_FMT_Y12_1X12,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 12, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SRGGB12, MEDIA_BUS_FMT_Y12_1X12,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 12, 0, 0 }, false, false, 1, 1, false },
> +
> + { V4L2_PIX_FMT_SBGGR16, MEDIA_BUS_FMT_Y16_1X16,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 16, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SGBRG16, MEDIA_BUS_FMT_Y16_1X16,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 16, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SGRBG16, MEDIA_BUS_FMT_Y16_1X16,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 16, 0, 0 }, false, false, 1, 1, false },
> + { V4L2_PIX_FMT_SRGGB16, MEDIA_BUS_FMT_Y16_1X16,
> + VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS,
> + 1, { 16, 0, 0 }, false, false, 1, 1, false },
> +
> + { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
> + VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> + VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
> + 1, { 10, 0, 0 }, false, false, 1, 1, false },
This doesn't seem right, the patch is changing the V4L2_PIX_FMT_RGB332.
> { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
> VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
> VI6_RPF_DSWAP_P_WDS,
--
Regards,
Laurent Pinchart
