Add base support for cameras for mt8365 platforms. This requires nodes for the sensor interface, camsv, and CSI receivers. Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> Signed-off-by: Julien Stephan <jstephan@xxxxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 125 +++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 9c91fe8ea0f969770a611f90b593683f93ff3e22..f3aae8d76cbece5779fe0b23139d594c0ea52579 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/mediatek,mt8365-power.h> +#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> / { compatible = "mediatek,mt8365"; @@ -704,6 +705,23 @@ ethernet: ethernet@112a0000 { status = "disabled"; }; + mipi_csi0: mipi-csi0@11c10000 { + compatible = "mediatek,mt8365-csi-rx"; + reg = <0 0x11c10000 0 0x2000>; + status = "disabled"; + num-lanes = <4>; + #phy-cells = <1>; + }; + + mipi_csi1: mipi-csi1@11c12000 { + compatible = "mediatek,mt8365-csi-rx"; + reg = <0 0x11c12000 0 0x2000>; + phy-type = <PHY_TYPE_DPHY>; + status = "disabled"; + num-lanes = <4>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -774,6 +792,113 @@ larb2: larb@15001000 { mediatek,larb-id = <2>; }; + seninf: seninf@15040000 { + compatible = "mediatek,mt8365-seninf"; + reg = <0 0x15040000 0 0x6000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; + clocks = <&camsys CLK_CAM_SENIF>, + <&topckgen CLK_TOP_SENIF_SEL>; + clock-names = "camsys", "top_mux"; + + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + + phys = <&mipi_csi0 PHY_TYPE_DPHY>, <&mipi_csi1>; + phy-names = "csi0", "csi1"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + seninf_camsv1_endpoint: endpoint { + remote-endpoint = + <&camsv1_endpoint>; + }; + }; + + port@5 { + reg = <5>; + seninf_camsv2_endpoint: endpoint { + remote-endpoint = + <&camsv2_endpoint>; + }; + }; + }; + }; + + camsv1: camsv@15050000 { + compatible = "mediatek,mt8365-camsv"; + reg = <0 0x15050000 0 0x0040>, + <0 0x15050208 0 0x0020>, + <0 0x15050400 0 0x0100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; + clocks = <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV0>; + clock-names = "cam", "camtg", "camsv"; + iommus = <&iommu M4U_PORT_CAM_IMGO>; + mediatek,larb = <&larb2>; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + camsv1_endpoint: endpoint { + remote-endpoint = <&seninf_camsv1_endpoint>; + }; + }; + }; + }; + + camsv2: camsv@15050800 { + compatible = "mediatek,mt8365-camsv"; + reg = <0 0x15050800 0 0x0040>, + <0 0x15050228 0 0x0020>, + <0 0x15050c00 0 0x0100>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; + clocks = <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV1>; + clock-names = "cam", "camtg", "camsv"; + iommus = <&iommu M4U_PORT_CAM_IMGO>; + mediatek,larb = <&larb2>; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + camsv2_endpoint: endpoint { + remote-endpoint = <&seninf_camsv2_endpoint>; + }; + }; + }; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt8365-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; -- 2.47.0