Hi Biju,
Thank you for the patch.
On Tue, Jul 09, 2024 at 02:51:43PM +0100, Biju Das wrote:
> The LCD controller is composed of Frame Compression Processor (FCPVD),
> Video Signal Processor (VSPD), and Display Unit (DU).
>
> It has DPI interface and supports a maximum resolution of WXGA along
> with 2 RPFs to support the blending of two picture layers and raster
> operations (ROPs).
>
> The DU module is connected to VSPD. Add RZ/G2UL DU support.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v1->v2:
> * No change.
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 9 ++++++++-
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 11 +++++++++++
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
> index 6e7aac6219be..b1812f947252 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
> @@ -28,6 +28,7 @@
> #include "rzg2l_du_vsp.h"
>
> #define DU_MCR0 0x00
> +#define DU_MCR0_DPI_OE BIT(0)
> #define DU_MCR0_DI_EN BIT(8)
>
> #define DU_DITR0 0x10
> @@ -216,9 +217,15 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc)
>
> static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start)
> {
> + struct rzg2l_du_crtc_state *rstate =
> + to_rzg2l_crtc_state(rcrtc->crtc.state);
I think you can avoid the line break here.
> struct rzg2l_du_device *rcdu = rcrtc->dev;
> + u32 val = DU_MCR0_DI_EN;
>
> - writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);
> + if (rstate->outputs == BIT(RZG2L_DU_OUTPUT_DPAD0))
> + val |= DU_MCR0_DPI_OE;
> +
> + writel(start ? val : 0, rcdu->mmio + DU_MCR0);
> }
>
> static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc)
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> index e5eca8691a33..34534441b7ec 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> @@ -25,6 +25,16 @@
> * Device Information
> */
>
> +static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
> + .channels_mask = BIT(0),
> + .routes = {
> + [RZG2L_DU_OUTPUT_DPAD0] = {
> + .possible_outputs = BIT(0),
> + .port = 1,
This may need to be port 0 depending on the outcome of the discussion on
the DT bindings.
> + },
> + },
> +};
> +
> static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> .channels_mask = BIT(0),
> .routes = {
> @@ -40,6 +50,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> };
>
> static const struct of_device_id rzg2l_du_of_table[] = {
> + { .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },
> { .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },
> { /* sentinel */ }
> };
--
Regards,
Laurent Pinchart
