From: Louis Kuo <louis.kuo@xxxxxxxxxxxx> This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in some Mediatek SoC, such as the mt8365 Signed-off-by: Louis Kuo <louis.kuo@xxxxxxxxxxxx> Signed-off-by: Phi-Bang Nguyen <pnguyen@xxxxxxxxxxxx> Link: https://lore.kernel.org/r/20230807094940.329165-2-jstephan@xxxxxxxxxxxx Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> Signed-off-by: Julien Stephan <jstephan@xxxxxxxxxxxx> --- .../bindings/media/mediatek,mt8365-seninf.yaml | 275 +++++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 282 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml new file mode 100644 index 000000000000..aeabea9f956a --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml @@ -0,0 +1,275 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Sensor Interface 3.0 + +maintainers: + - Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> + - Julien Stephan <jstephan@xxxxxxxxxxxx> + - Andy Hsieh <andy.hsieh@xxxxxxxxxxxx> + +description: + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in + multiple MediaTek SoCs. It can support up to three physical CSI-2 input ports, + configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC. + On the output side, SENINF can be connected either to CAMSV instance or + to the internal ISP. CAMSV is used to bypass the internal ISP processing + in order to connect either an external ISP, or a sensor (RAW, YUV). + +properties: + compatible: + const: mediatek,mt8365-seninf + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Seninf camsys clock + - description: Seninf top mux clock + + clock-names: + items: + - const: camsys + - const: top_mux + + phys: true + + phy-names: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0 or CSI0A port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI1 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI2 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0B port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 2 + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for cam0 + + port@5: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for cam1 + + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv0 + + port@7: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv1 + + port@8: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv2 + + port@9: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv3 + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + - port@6 + - port@7 + - port@8 + - port@9 + +required: + - compatible + - interrupts + - clocks + - clock-names + - power-domains + - ports + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: mediatek,mt8365-seninf +then: + properties: + phys: + minItems: 2 + maxItems: 2 + description: + phandle to the PHYs connected to CSI0/A, CSI1, CSI0B + + phy-names: + description: + list of PHYs names + minItems: 2 + maxItems: 2 + items: + type: string + enum: + - csi0 + - csi1 + - csi0b + uniqueItems: true + +examples: + - | + #include <dt-bindings/clock/mediatek,mt8365-clk.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/power/mediatek,mt8365-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + csi: csi@15040000 { + compatible = "mediatek,mt8365-seninf"; + reg = <0 0x15040000 0 0x6000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; + clocks = <&camsys CLK_CAM_SENIF>, + <&topckgen CLK_TOP_SENIF_SEL>; + clock-names = "camsys", "top_mux"; + + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + + phys = <&mipi_csi0 PHY_TYPE_DPHY>, <&mipi_csi1>; + phy-names = "csi0", "csi1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + seninf_in1: endpoint { + clock-lanes = <2>; + data-lanes = <1 3 0 4>; + remote-endpoint = <&isp1_out>; + }; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + seninf_camsv1_endpoint: endpoint { + remote-endpoint = <&camsv1_endpoint>; + }; + }; + + port@5 { + reg = <5>; + seninf_camsv2_endpoint: endpoint { + remote-endpoint = <&camsv2_endpoint>; + }; + }; + + port@6 { + reg = <6>; + }; + + port@7 { + reg = <7>; + }; + + port@8 { + reg = <8>; + }; + + port@9 { + reg = <9>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d6c90161c7bf..6bd7df1c3e08 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14158,6 +14158,13 @@ M: Sean Wang <sean.wang@xxxxxxxxxxxx> S: Maintained F: drivers/char/hw_random/mtk-rng.c +MEDIATEK ISP3.0 DRIVER +M: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> +M: Julien Stephan <jstephan@xxxxxxxxxxxx> +M: Andy Hsieh <andy.hsieh@xxxxxxxxxxxx> +S: Supported +F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml + MEDIATEK SMI DRIVER M: Yong Wu <yong.wu@xxxxxxxxxxxx> L: linux-mediatek@xxxxxxxxxxxxxxxxxxx (moderated for non-subscribers) -- 2.45.1
