On 09/04/2024 13:27, Bryan O'Donoghue wrote:
> On 08/04/2024 16:39, Marc Gonzalez wrote:
>
>> On 29/02/2024 16:32, Vikash Garodia wrote:
>>
>>> Not completely sure on these configurations, but certainly both the
>>> video_subcore0_gdsc and video_subcore1_gdsc should be configured in
>>> hardware control mode in the gdsc configuration.
>>
>> Still trying to land support for venus decoder on msm8998 in mainline.
>>
>> This is the patch I have at the moment:
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> index 4dfe2d09ac285..67b8374ddf02f 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> @@ -3010,6 +3010,55 @@ mdss_dsi1_phy: phy@c996400 {
>> };
>> };
>>
>> + venus: video-codec@cc00000 {
>> + compatible = "qcom,msm8998-venus";
>> + reg = <0x0cc00000 0xff000>;
>> + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&mmcc VIDEO_TOP_GDSC>;
>> + clocks = <&mmcc VIDEO_CORE_CLK>,
>> + <&mmcc VIDEO_AHB_CLK>,
>> + <&mmcc VIDEO_AXI_CLK>,
>> + <&mmcc VIDEO_MAXI_CLK>;
>> + clock-names = "core", "iface", "bus", "mbus";
>> + iommus = <&mmss_smmu 0x400>,
>> + <&mmss_smmu 0x401>,
>> + <&mmss_smmu 0x40a>,
>> + <&mmss_smmu 0x407>,
>> + <&mmss_smmu 0x40e>,
>> + <&mmss_smmu 0x40f>,
>> + <&mmss_smmu 0x408>,
>> + <&mmss_smmu 0x409>,
>> + <&mmss_smmu 0x40b>,
>> + <&mmss_smmu 0x40c>,
>> + <&mmss_smmu 0x40d>,
>> + <&mmss_smmu 0x410>,
>> + <&mmss_smmu 0x411>,
>> + <&mmss_smmu 0x421>,
>> + <&mmss_smmu 0x428>,
>> + <&mmss_smmu 0x429>,
>> + <&mmss_smmu 0x42b>,
>> + <&mmss_smmu 0x42c>,
>> + <&mmss_smmu 0x42d>,
>> + <&mmss_smmu 0x411>,
>> + <&mmss_smmu 0x431>;
>> + memory-region = <&venus_mem>;
>> + status = "disabled";
>> +
>> + video-decoder {
>> + compatible = "venus-decoder";
>> + clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
>> + clock-names = "core";
>> + power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
>> + };
>> +
>> + video-encoder {
>> + compatible = "venus-encoder";
>> + clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
>> + clock-names = "core";
>> + power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
>> + };
>> + };
>> +
>> mmss_smmu: iommu@cd00000 {
>> compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
>> reg = <0x0cd00000 0x40000>;
>> diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c
>> index ce206b7097541..42e0c580e093d 100644
>> --- a/drivers/media/platform/qcom/venus/core.c
>> +++ b/drivers/media/platform/qcom/venus/core.c
>> @@ -587,6 +587,47 @@ static const struct venus_resources msm8996_res = {
>> .fwname = "qcom/venus-4.2/venus.mbn",
>> };
>>
>> +static const struct freq_tbl msm8998_freq_table[] = {
>> + { 1944000, 520000000 }, /* 4k UHD @ 60 (decode only) */
>> + { 972000, 520000000 }, /* 4k UHD @ 30 */
>> + { 489600, 346666667 }, /* 1080p @ 60 */
>> + { 244800, 150000000 }, /* 1080p @ 30 */
>> + { 108000, 75000000 }, /* 720p @ 30 */
>> +};
>> +
>> +/*
>> + * https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/caf_migration/kernel.lnx.4.4.r38-rel/arch/arm/boot/dts/qcom/msm8998-vidc.dtsi
>> + */
>> +static const struct reg_val msm8998_reg_preset[] = {
>> + { 0x80124, 0x00000003 },
>> + { 0x80550, 0x01111111 },
>> + { 0x80560, 0x01111111 },
>> + { 0x80568, 0x01111111 },
>> + { 0x80570, 0x01111111 },
>> + { 0x80580, 0x01111111 },
>> + { 0x80588, 0x01111111 },
>> + { 0xe2010, 0x00000000 },
>> +};
>> +
>> +static const struct venus_resources msm8998_res = {
>> + .freq_tbl = msm8998_freq_table,
>> + .freq_tbl_size = ARRAY_SIZE(msm8998_freq_table),
>> + .reg_tbl = msm8998_reg_preset,
>> + .reg_tbl_size = ARRAY_SIZE(msm8998_reg_preset),
>> + .clks = { "core", "iface", "bus", "mbus" },
>> + .clks_num = 4,
>> + .vcodec0_clks = { "core" },
>> + .vcodec1_clks = { "core" },
>> + .vcodec_clks_num = 1,
>> + .max_load = 2563200,
>> + .hfi_version = HFI_VERSION_3XX,
>> + .vmem_id = VIDC_RESOURCE_NONE,
>> + .vmem_size = 0,
>> + .vmem_addr = 0,
>> + .dma_mask = 0xddc00000 - 1,
>> + .fwname = "qcom/venus-4.4/venus.mbn",
>> +};
>> +
>> static const struct freq_tbl sdm660_freq_table[] = {
>> { 979200, 518400000 },
>> { 489600, 441600000 },
>> @@ -893,6 +934,7 @@ static const struct venus_resources sc7280_res = {
>> static const struct of_device_id venus_dt_match[] = {
>> { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, },
>> { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, },
>> + { .compatible = "qcom,msm8998-venus", .data = &msm8998_res, },
>> { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, },
>> { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, },
>> { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, },
>> diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c
>> index f9437b6412b91..abdc578ce988e 100644
>> --- a/drivers/media/platform/qcom/venus/hfi_venus.c
>> +++ b/drivers/media/platform/qcom/venus/hfi_venus.c
>> @@ -945,6 +945,7 @@ static int venus_sys_set_default_properties(struct venus_hfi_device *hdev)
>> dev_warn(dev, "setting idle response ON failed (%d)\n", ret);
>> }
>>
>> + venus_fw_low_power_mode = false;
>
> So instead of this workaround, @Vikash is asking for HW_CTRL similar to
> what we have in 8996
>
> 8996 has a top-level "magic" GDSC which 8998 doesn't appear to have.
>
> I think the CXC stuff would still be valid.
>
> diff --git a/drivers/clk/qcom/mmcc-msm8998.c
> b/drivers/clk/qcom/mmcc-msm8998.c
> index 1180e48c687ac..275fb3b71ede4 100644
> --- a/drivers/clk/qcom/mmcc-msm8998.c
> +++ b/drivers/clk/qcom/mmcc-msm8998.c
> @@ -2535,6 +2535,8 @@ static struct clk_branch vmem_ahb_clk = {
>
> static struct gdsc video_top_gdsc = {
> .gdscr = 0x1024,
> + .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
> + .cxc_count = 3,
> .pd = {
> .name = "video_top",
> },
> @@ -2543,20 +2545,26 @@ static struct gdsc video_top_gdsc = {
>
> static struct gdsc video_subcore0_gdsc = {
> .gdscr = 0x1040,
> + .cxcs = (unsigned int []){ 0x1048 },
> + .cxc_count = 1,
> .pd = {
> .name = "video_subcore0",
> },
> .parent = &video_top_gdsc.pd,
> .pwrsts = PWRSTS_OFF_ON,
> + .flags = HW_CTRL,
> };
>
> static struct gdsc video_subcore1_gdsc = {
> .gdscr = 0x1044,
> + .cxcs = (unsigned int []){ 0x104c },
> + .cxc_count = 1,
> .pd = {
> .name = "video_subcore1",
> },
> .parent = &video_top_gdsc.pd,
> .pwrsts = PWRSTS_OFF_ON,
> + .flags = HW_CTRL,
> };
>
> Can you give it a try ?
Looks like your patch DOES fix the issue!
References (mostly) for myself
static struct gdsc video_top_gdsc = {
.gdscr = 0x1024,
.cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
static struct gdsc video_subcore0_gdsc = {
.gdscr = 0x1040,
.cxcs = (unsigned int []){ 0x1048 },
static struct gdsc video_subcore1_gdsc = {
.gdscr = 0x1044,
.cxcs = (unsigned int []){ 0x104c },
GDSCR = Globally Distributed Switch Controller Register
https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/caf_migration/kernel.lnx.4.4.r38-rel/include/dt-bindings/clock/msm-clocks-hwio-8998.h
0x1024 = undocumented = MMSS_VIDEO GDSCR
0x1028 = MMSS_VIDEO_CORE_CBCR
0x1030 = MMSS_VIDEO_AHB_CBCR
0x1034 = MMSS_VIDEO_AXI_CBCR
0x1038 = MMSS_VIDEO_MAXI_CBCR
0x1040 = undocumented = MMSS_VIDEO_SUBCORE0 GDSCR
0x1044 = undocumented = MMSS_VIDEO_SUBCORE1 GDSCR
0x1048 = MMSS_VIDEO_SUBCORE0_CBCR
0x104c = MMSS_VIDEO_SUBCORE1_CBCR
On msm8996
static struct gdsc venus_gdsc = {
.gdscr = 0x1024,
.cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x1040,
.cxcs = (unsigned int []){ 0x1048 },
static struct gdsc venus_core1_gdsc = {
.gdscr = 0x1044,
.cxcs = (unsigned int []){ 0x104c },
https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/caf_migration/kernel.lnx.4.4.r38-rel/include/dt-bindings/clock/msm-clocks-hwio-8996.h
0x1028 = MMSS_VIDEO_CORE_CBCR = MMSS_VIDEO_CXO_CBCR
0x1030 = MMSS_VIDEO_AHB_CBCR
0x1034 = MMSS_VIDEO_AXI_CBCR
0x1038 = MMSS_VIDEO_MAXI_CBCR
0x1048 = MMSS_VIDEO_SUBCORE0_CBCR
0x104c = MMSS_VIDEO_SUBCORE1_CBCR
Registers of interest are mapped identically in msm8996 & msm8998.
Therefore, it makes sense for the code to be identical.
Regards
