Currently documentation related to disabling of clock do not state
it is synchronous or asynchronous clock gating. So, make it clear it is
driver dependent.
The clk_disable_unprepare() doesn't guarantee that a clock is gated after
the execution as it is driver dependent. The Renesas and most of the other
platforms don't wait until clock is stopped because of performance reason.
But these platforms wait while turning on the clock.
The normal case for shutting down the clock is unbind/close/suspend or
error paths in the driver. Not waiting for the shutting down the clock
will improve the suspend time.
But on RZ/G2L Camera Data Receiving Unit (CRU) IP, initially the vclk is
on. Before enabling link reception, we need to wait for vclk to be off
and after enabling reception, we need to turn the vlck on. Special cases
like this requires a sync API for clock gating.
Add clk_poll_disable_unprepare() to poll the clock gate operation that
guarantees gating of clk after the execution.
RFC->v2:
* Updated cover letter description and header.
* Created patch#1 for updating existing documentation.
* Renamed clk_disable_unprepare_sync()-->clk_poll_disable_unprepare()
* Redesigned to make use of __clk_is_enabled() to poll the clock gating.
Biju Das (3):
clk: Update API documentation related to clock disable
clk: Add clk_poll_disable_unprepare()
media: platform: rzg2l-cru: rzg2l-video: Use
clk_poll_disable_unprepare()
drivers/clk/clk.c | 26 +++++++++-
.../platform/renesas/rzg2l-cru/rzg2l-csi2.c | 5 +-
include/linux/clk-provider.h | 3 +-
include/linux/clk.h | 49 ++++++++++++++++++-
4 files changed, 79 insertions(+), 4 deletions(-)
--
2.25.1
