Hi CK,
Thanks for the reivews.
On Tue, 2023-12-26 at 03:20 +0000, CK Hu (胡俊光) wrote:
> Hi, Jason:
>
> On Sun, 2023-12-24 at 02:29 +0800, Jason-JH.Lin wrote:
> > Add secure layer config support for ovl_adaptor and sub driver
> > mdp_rdma.
> >
> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@xxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 15
> > +++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 11 ++++++++---
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 2 ++
> > 5 files changed, 27 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 77054adcd9cf..ec9746767468 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -117,6 +117,7 @@ void mtk_ovl_adaptor_clk_disable(struct device
> > *dev);
> > void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +u64 mtk_ovl_adaptor_get_sec_port(struct mtk_ddp_comp *comp,
> > unsigned
> > int idx);
> > void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > struct mtk_plane_state *state,
> > struct cmdq_pkt *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > index 6bf6367853fb..f419c2e70ba3 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -83,6 +83,18 @@ static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> > };
> >
> > +static const u64 ovl_adaptor_sec_port[] = {
> > + BIT_ULL(CMDQ_SEC_VDO1_DISP_RDMA_L0),
> > + BIT_ULL(CMDQ_SEC_VDO1_DISP_RDMA_L1),
> > + BIT_ULL(CMDQ_SEC_VDO1_DISP_RDMA_L2),
> > + BIT_ULL(CMDQ_SEC_VDO1_DISP_RDMA_L3),
> > +};
> > +
> > +u64 mtk_ovl_adaptor_get_sec_port(struct mtk_ddp_comp *comp,
> > unsigned
> > int idx)
> > +{
> > + return ovl_adaptor_sec_port[idx];
> > +}
> > +
> > void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > struct mtk_plane_state *state,
> > struct cmdq_pkt *cmdq_pkt)
> > @@ -141,6 +153,9 @@ void mtk_ovl_adaptor_layer_config(struct device
> > *dev, unsigned int idx,
> > rdma_config.pitch = pending->pitch;
> > rdma_config.fmt = pending->format;
> > rdma_config.color_encoding = pending->color_encoding;
> > + rdma_config.source_size = (pending->height - 1) * pending-
> > > pitch +
> >
> > + pending->width * fmt_info->cpp[0];
> > + rdma_config.is_secure = state->pending.is_secure;
> > mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> >
> > if (use_dual_pipe) {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 6aed7647dfc0..9b7fe34df9a6 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -445,6 +445,7 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ovl_adaptor = {
> > .remove = mtk_ovl_adaptor_remove_comp,
> > .get_formats = mtk_ovl_adaptor_get_formats,
> > .get_num_formats = mtk_ovl_adaptor_get_num_formats,
> > + .get_sec_port = mtk_ovl_adaptor_get_sec_port,
> > };
> >
> > static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > =
> > {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > index c3adaeefd551..a164ba82d022 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > @@ -94,6 +94,7 @@ struct mtk_mdp_rdma {
> > void __iomem *regs;
> > struct clk *clk;
> > struct cmdq_client_reg cmdq_reg;
> > + resource_size_t regs_pa;
> > };
> >
> > static unsigned int rdma_fmt_convert(unsigned int fmt)
> > @@ -198,9 +199,12 @@ void mtk_mdp_rdma_config(struct device *dev,
> > struct mtk_mdp_rdma_cfg *cfg,
> > else
> > mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > > regs,
> >
> > MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
> > -
> > - mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv-
> > > regs,
> >
> > - MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
> > + if (cfg->is_secure)
> > + mtk_ddp_sec_write(cmdq_pkt, priv->regs_pa +
> > MDP_RDMA_SRC_BASE_0,
> > + cfg->addr0, CMDQ_IWC_H_2_MVA, 0, cfg-
> > > source_size, 0);
>
> In OVL, there is one bit that control OVL hardware could access
> secure
> buffer or not. Why mdp rdma has no this bit?
>
> Regards,
> CK
>
Yes, that's different HW design for OVL.
Because OVL has 4 layers, we can't witch the whole larb port to secure
like MDP_RDMA. So that OVL can support normal buffer input and secure
buffer input at the same time.
Regards,
Jason-JH.Lin
