The default behavior for a base address change is to do it automatically
after a DMA completion. This can lead to the situation, were one
corrupted frame, with less lines than configured, results in all
following frames being corrupted as well, due to a missing
re-synchronization to the beginning of the next frame.
Fix this by configuring the base address switch to be synced with the
start of frame event.
Currently this is already implemented for the parallel interface. To
have it with MIPI as well, simply configure it unconditionally.
Tested on i.MX 8MM.
Signed-off-by: Stefan Riedmüller <s.riedmueller@xxxxxxxxx>
---
drivers/media/platform/nxp/imx7-media-csi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/nxp/imx7-media-csi.c b/drivers/media/platform/nxp/imx7-media-csi.c
index 15049c6aab37..0c9e3f01e96d 100644
--- a/drivers/media/platform/nxp/imx7-media-csi.c
+++ b/drivers/media/platform/nxp/imx7-media-csi.c
@@ -529,13 +529,13 @@ static void imx7_csi_configure(struct imx7_csi *csi,
stride = out_pix->width;
}
+ cr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
+ BIT_BASEADDR_CHG_ERR_EN;
+
if (!csi->is_csi2) {
cr1 = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL
| BIT_FCC | BIT_MCLKDIV(1) | BIT_MCLKEN;
- cr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
- BIT_BASEADDR_CHG_ERR_EN;
-
if (out_pix->pixelformat == V4L2_PIX_FMT_UYVY ||
out_pix->pixelformat == V4L2_PIX_FMT_YUYV)
width *= 2;
--
2.25.1
