Support for MT8195 RDMA has been added, allowing for the configuration of multiple MDP3 pipes. Furthermore, this particular device does not require sharing SRAM with RSZ. Signed-off-by: Moudy Ho <moudy.ho@xxxxxxxxxxxx> --- .../media/mediatek,mdp3-rdma-8195.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-8195.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-8195.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-8195.yaml new file mode 100644 index 000000000000..f10139aec3c5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-8195.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma-8195.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8195 Read Direct Memory Access + +maintainers: + - Matthias Brugger <matthias.bgg@xxxxxxxxx> + - Moudy Ho <moudy.ho@xxxxxxxxxxxx> + +description: | + MediaTek Read Direct Memory Access(RDMA) component used to do read DMA. + This type of component is configured when there are multiple MDP3 pipelines + that belong to different MMSYS subsystems. + It contains one line buffer to store the sufficient pixel data, and + must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml + for details. + +allOf: + - $ref: mediatek,mdp3-rdma-common.yaml# + +properties: + compatible: + items: + - const: mediatek,mt8195-mdp3-rdma + + clocks: + maxItems: 1 + + mboxes: + maxItems: 5 + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + #include <dt-bindings/power/mt8195-power.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + + dma-controller@14001000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0x14001000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, + <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; + mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, + <&gce1 13 CMDQ_THR_PRIO_1>, + <&gce1 14 CMDQ_THR_PRIO_1>, + <&gce1 21 CMDQ_THR_PRIO_1>, + <&gce1 22 CMDQ_THR_PRIO_1>; + #dma-cells = <1>; + }; -- 2.18.0
